1. Field of the Invention
The present invention relates to a superconducting device and a method of manufacturing the same.
2. Description of the Related Art
A superconducting device with a Josephson junction is a device expected to be practically applied to an SFQ (Single Flux Quantum) circuit using a single flux quantum as an information medium, a SQUID (Superconducting Quantum Interference Device) that is a highly-sensitive magnetic field sensor, or the like (See JP-A Nos. Hei 8-330641 and Hei 9-260734.).
Many methods of manufacturing the superconducting device with the Josephson junction have been proposed. (See JP-A Nos. Hei 8-330641, Hei 9-260734, 2000-150974 and 2006-66783.) The Josephson junctions are classified into several types according to their forming methods.
When a superconducting thin film is superposed on a bicrystal substrate formed of two single crystal substrates bonded together with their crystallographic orientation obliquely aligned, a grain boundary is formed in the thin film along a junction line (a bicrystal line) between the two substrates. The grain boundary forms a barrier layer of a Josephson junction, and thereby the Josephson junction is formed on the substrate.
When an oxide superconducting thin film is superposed on a surface of a bicrystal substrate, a grain boundary is formed in the thin film along the bicrystal line. This grain boundary forms a barrier layer of a Josephson junction, and thereby the Josephson junction (a step-edge Josephson junction) is formed on the substrate.
Besides the Josephson junction formed by using the bicrystal substrate or the step edge to form the grain boundary as the barrier layer of the Josephson junction, the Josephson junctions include a ramp-edge type Josephson junction fabricated by forming a ramp edge on a superconducting thin film, amorphizing the edge surface, forming a superconducting layer on the edge surface, and then recrystallizing the amorphous edge surface to form a barrier layer, as described in JP-A Nos. 2000-150974 and 2006-66783.
However, the superconducting devices disclosed in JP-A Nos. Hei 8-330641, Hei 9-260734, 2000-150974 and 2006-66783 cannot be used to fabricate a larger-scale SFQ circuit or to fabricate a SQUID of higher sensitivity, because they include only one layer of a superconducting circuit pattern formed on the substrate.
Fabrication of a larger-scale SFQ or SQUID circuit requires a superconducting device of a multilayer structure in which a plurality of superconducting circuit patterns are superposed on one another. However, good characteristics cannot be obtained even if the multilayer structure is fabricated by depositing an insulating thin film and another oxide superconducting thin film on the Josephson junction formed on the bicrystal substrate. Descriptions will be given of the reasons for this with reference to the conventional technologies.
FIGS. 1A and 1B illustrate a conventional fabrication method. FIGS. 1A and 1B show a cross-sectional view and a plan view, respectively. A superconducting thin film 3a, which is formed by forming a single-layer superconducting thin film, and then by forming a circuit pattern thereon, is superposed on an insulating bicrystal substrate 1. Thereby, a superconducting thin film grain boundary 33 is formed on a bicrystal line 2. The grain boundary 33 forms a barrier layer of a Josephson junction, and thus a SQUID or another circuit can be fabricated. In this case, only a circuit of a simple structure can be fabricated because only a single superconducting layer is formed.
To deal with this problem, some attempts have been made to fabricate the multilayer structure by depositing an insulating thin film and a second-level superconducting thin film.
FIGS. 2A and 2B illustrate a conventional method of fabricating a multilayer structure using a bicrystal substrate. FIGS. 2A and 2B show a cross-sectional view and a plan view, respectively, of the multilayer structure. A Josephson junction is formed in a first-level superconducting thin film 3a, as in the case of the structure shown in FIGS. 1A and 1B. When an insulating layer 5 and a second-level superconducting layer 8 are deposited on the first-level superconducting thin film 3a, elements that constitute an insulator and the like are diffused, during a substrate heating process essential for deposition, into the grain boundary on the bicrystal substrate which functions as the barrier layer of the Josephson junction. This leads to deterioration in junction characteristics of the previously-formed Josephson junction.
FIGS. 3A and 3B illustrate a conventional method of fabricating a multilayer structure using a step-edge substrate. FIGS. 3A and 3B show a cross-sectional view and a plan view, respectively, of a multilayer structure. A Josephson junction is formed in a first-level superconducting thin film 3a, as in the case of the structure shown in FIGS. 2A and 2B. When a insulating layer 5a and a second-level superconducting layer 8a are deposited on the first-level superconducting thin film 3a, elements that constitute an insulator or the like are diffused, during the substrate heating process essential for deposition, into the grain boundary 33 on the step edge 34 which functions as the barrier layer of the Josephson junction. This leads to deterioration in the junction characteristics of the previously-formed Josephson junction.
In these cases, a superconducting circuit of a complicated structure can be fabricated, but circuit characteristics are not good because the junction characteristics of the Josephson junction are thus deteriorated.
The junction characteristics of a ramp-edge junction of a surface-engineered type similarly change, when a Josephson junction is formed and then an insulating thin film and an oxide superconducting thin film are deposited on the Josephson junction. The reason is that this leads to a change in a crystal structure of the barrier of the Josephson junction during the heating process. A superconducting circuit that can be correctly operated cannot be fabricated, when the characteristics of the Josephson junction are changed, for example, when the critical current passing through the junction deviates from a designed value.
Next, detailed descriptions will be given of the conventional technologies using the ramp-edge junction of the surface-engineered type.
FIGS. 4A and 4B illustrate a cross section of a circuit using the ramp-edge junction of a surface-engineered type having the simplest structure. FIGS. 4A and 4B show a cross-sectional view and a plan view, respectively, of the multilayer structure. A first-level first superconducting layer 23 and a first insulating layer 24 are deposited on an insulating substrate 20, and then a circuit pattern is formed thereon. Thereby, an amorphous layer 23c, which is formed by the amorphous first superconducting layer 23, is formed on a ramp-edge 23b. 
After a second-level second superconducting layer 31 is deposited, the amorphous layer is recrystallized due to the heating of the substrate for forming the second superconducting layer, and thereby changes into a barrier layer 23d for a ramp-edge junction. The barrier layer 23d for a ramp-edge junction forms the barrier layer of the Josephson junction, and thereby the Josephson junction can be formed. Then, various circuits can be fabricated.
In this case, the junction characteristics do not change because of the absence of the heating process after forming the junction. However, a pattern intersecting the inclined surface 23b of the first superconducting layer cannot be formed since the inclined surface 23b is exposed except for a portion thereof for forming the junction. This configuration prohibits installation of wiring or the like on the insulating layer 24. Accordingly, this method can be said as the one that significantly decreases the degree of freedom of forming circuit elements, wiring or the like.
FIGS. 5A and 5B illustrate a structure in which a ground plane 21 of an oxide superconducting thin film is disposed below a junction layer. FIGS. 5A and 5B show a cross-sectional view and a plan view, respectively, of a multilayer structure. In this case, as in the case of the structure shown in FIGS. 4A and 4B, a wiring layer or the like cannot be disposed above the junction layer, and thereby it is difficult to implement a complicated circuit, although the junction characteristics do not change because of the absence of the heating process after forming the junction.
FIG. 5C illustrates a structure in which the ground plane 21 of the oxide superconducting thin film is disposed above the junction layer. Also in this case, it is difficult to implement a complicated circuit because of the absence of the wiring layer or the like. Moreover, the ground plane 21, which is the oxide superconducting thin film, and a second insulating layer 27 are deposited above the junction after forming the junction. For this reason, the junction is adversely affected by the influence of the heating process, and the junction characteristics are deteriorated due to a subtle change in the crystal structure of the barrier.
FIGS. 6A and 6B illustrate a structure in which the ground plane 21 of an oxide superconducting thin film is disposed below a junction layer, and in which an upper wiring structure is formed above the junction layer by depositing a third-level third superconducting layer 32 and a second insulating layer 27. FIGS. 6A and 6B show a cross-sectional view and a plan view, respectively, of a multilayer structure. For this ramp-edge junction circuit, it is necessary to form an upper superconducting electrode using a part of an inclined surface 23b, and then to coat the rest of the inclined surface 23b with an insulating film, in order to form a circuit pattern within an island region where the inclined surface 23b is formed, and then to connect the pattern to the outside of the island region. In this case, a complicated circuit can be implemented since an upper wiring layer can be fabricated. However, the junction is adversely affected by the influence of the heating process since the third-level third superconducting layer 32 and the second insulating layer 27 are deposited on the junction after forming the junction. For this reason, the junction characteristics change due to the subtle change in the crystal structure of the barrier.
To fabricate a large-scale SFQ circuit or a complicated SQUID circuit, it is desirable that a device have a multilayer structure, and that a circuit element, such as wiring or a coil, be fabricated above the insulating layer 24 in the vicinity of a junction.
As described above, however, the use of the conventional technologies to implement the multilayer structure, such as the wiring layer, above the Josephson junction after forming the Josephson junction leads to a problem such as impairment of normal circuit operation due to the deterioration in the characteristics of the Josephson junction with the grain boundary, or due to the change in the characteristics of the ramp-edge Josephson junction of the surface-engineered type.
In other words, it is difficult, with the conventional technologies, to superpose a superconducting layer and an insulating layer on a superconducting layer having a Josephson junction without a deterioration or change in the junction characteristics of the Josephson junction, as well as to remove restrictions on the disposition of circuit elements, such as wiring and a coil, on the uppermost layer, and therefore to fabricate a large-scale superconducting device with excellent circuit characteristics.